1. Field of the Invention
The present invention generally relates to a speed regulating apparatus for motors, more particularly to a technique applicable to speed control of spindle motors, to a motor speed regulating circuit effectively applicable to a semiconductor integrated circuit (IC) device dedicated to a unit for controlling mechanisms of drives such as floppy disk drives, hard disk drives, and optical disk drives, and to a storage medium drive using the motor speed regulating circuit.
2. Description of the Related Art
In a floppy disk drive (FDD) or a hard disk drive (HDD), a rotation speed of a motor for driving a storage medium disk is detected by a tachometer generator as a function of frequency, and in accordance with the detected frequency the speed of the motor is subjected to a feedback control.
The motor speed regulating apparatus of this type has been proposed, for example, in JP-A-61-154492 (Document (1)) in which two counters count clocks synchronously with the start and end of each half cycle of a speed signal of a motor detected as a function of frequency. This is done in order to always detect a difference from a standard time. A speed control voltage is adjusted in accordance with the detected time difference for the feedback control of the motor speed.
The cost and consumption power of a motor and its peripheral circuit used in an information processing apparatus amounts to a large percentage. Thus, it is a significant issue to reduce the cost and consumption power. In the case of a motor speed regulating circuit, the cost and consumption power of counters for generating a standard time corresponding to a standard speed also occupy a large percentage.
In an FDD, counters for generating a standard time are provided in the speed regulating circuit without using CPU software counters. Therefore, the cost and consumption power depend largely on the number of hardware counters.
A speed regulating circuit, in which only one counter is used to count clocks synchronously with one of the start and end of each half cycle of a speed signal, is described in JP-A-63-310391 (Document (2)) and JP-A-55-109183 (Document (3)).